Solution Briefs

Reconfigurable Accelerated RAN For 5G Mobile Network Operators

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PROBLEM To meet demands of 5G, Radio Access Network (RAN) architectures are undergoing a transformation to increase deployment flexibility and performance, while continually curbing total cost of ownership. This transformation includes the capability to place selected functions closer to the edge network and the ability to increase RAN resilience. Network Function Virtualization (NFV) is emerging as a viable approach to increase network flexibility and reduce time to market for new services. The current NFV deployment model in RAN architectures utilizes standard x86 servers with software only. But this approach introduces major performance bottlenecks due to the heavy application workloads including the compute intensive Packet Data Convergence Protocol (PDCP), managing the ciphering and integrity protection, and other mobile application workloads. SOLUTION The partnership between Napatech, Radisys, Xilinx and Silex Inside has bred a best-in-class solution that enables standard servers to perform a significant part of the processing needed on the edge network. By offloading CPU-intensive functions such as virtual switching and PDCP ciphering tasks from the general-purpose processors, the solution successfully delivers a 10x performance increase. SOLUTION DESCRIPTION RECONFIGURABLE ACCELERATED RAN FOR 5G MOBILE NETWORK OPERATORS With 5G on the horizon, mobile network operators are hungry to make the shift from proprietary hardware to standard server platforms. In many instances, however, standard platforms struggle to meet network performance requirements due to the CPU-intensive demands of mobile applications. To realize the promise of 5G, a new level of performance is therefore required at the hardware layer. Napatech's Reconfigurable Accelerated RAN solution allows network operators to reimagine their infrastructure by alleviating CPU bottlenecks and increasing system performance by a factor 10. Reconfigurable Accelerated RAN Solution Stack. Virtual eNodeB PDCP/GTP Air Ciphering + OVS Wire Encryption (IPSec) PMD API VM UE Core Network Network Interface Network Interface Network Interface CPU PCIe VNF Virtual Switch Guest OS PMD Control VNF FPGA Runtime FPGA HAL Crypto API Packet and Flow Classication NIC NIC Napatech FPGA-based Smart NIC Hypervisor (KVM) Open Virtual Switch (OVS) Ofoad Acceleration PDCP and Air Ciphering Acceleration IPSec Ofoad OpenStack & OpenFlow Integration Accelration for PDCP, OVS and ZUC apatech FPGA-based Smart N

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